Add ability to constrain flop harness to specific side of PBlock#1318
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clavin-xlnx merged 18 commits intoXilinx:array_builderfrom Dec 3, 2025
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…k to improve routability. Also unroute top-level I/O nets that exit the pblock. Signed-off-by: Andrew Butt <Andrew.Butt@amd.com>
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Signed-off-by: Andrew Butt <Andrew.Butt@amd.com>
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Signed-off-by: Andrew Butt <Andrew.Butt@amd.com>
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Signed-off-by: Andrew Butt <Andrew.Butt@amd.com>
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Signed-off-by: Andrew Butt <Andrew.Butt@amd.com>
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Signed-off-by: Andrew Butt <Andrew.Butt@amd.com>
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Signed-off-by: Andrew Butt <Andrew.Butt@amd.com>
…the same slice as a ground source Signed-off-by: Andrew Butt <Andrew.Butt@amd.com>
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test/src/com/xilinx/rapidwright/design/tools/TestInlineFlopTools.java
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Signed-off-by: Andrew Butt <Andrew.Butt@amd.com>
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I added a somewhat unrelated change too where I removed some unnecessary prints that happen when parsing the XDC. They are just annoying when running tests that parse the XDC and don't really add anything. |
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Signed-off-by: Andrew Butt <Andrew.Butt@amd.com>
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To ensure routability of ArrayBuilder designs, it is important that there is a routing path from a precompiled module in the direction of the input of the next precompiled module. A side map is provided to PerformanceExplorer which specifies which side of the pblock a given top-level I/O should have its flop placed on. Also unroutes top-level I/O nets that exit the pblock to prevent node overlaps between blocks placed near each other in the array.